1. Field of the Invention
The present invention relates to a delay circuit, and more specifically, to a delay circuit that has a low dependence on the operating environment such as a power-supply voltage and an operating temperature.
2. Description of the Background Art
In a semiconductor device, delay circuits are used in various portions in order to delay the signals by prescribed period of time. A delay circuit is used for such purpose as adjusting the timing of a signal. For instance, a delay circuit is used as follows in a processing system including a clock synchronous semiconductor memory device that performs signal/data transfer in synchronization with a clock signal. Normally, in a processing system, the distance between a processor (or a memory controller) and the respective clock synchronous semiconductor memory devices varies from device to device. If the clock signal is a common clock signal such as a system clock, the timing, relative to the clock signal, at which a signal/data from a semiconductor memory device arrives at the processor varies depending on the distance between each semiconductor memory device and the processor (or the memory controller). In order to match the arrival timing of the signal/data relative to the clock signal throughout all the semiconductor memory devices by compensating for the time difference in the arrival timing, a delay circuit such as one called vernier is employed within the semiconductor memory devices. Using this vernier, the output timings of the signal/data is adjusted so as to match the timings of the signal arrival at the processor (or the memory controller) among semiconductor memory devices.
FIG. 55 is a diagram representing an example of the arrangement of a conventional delay circuit. In FIG. 55, the delay circuit includes an inverter circuit 900 for inverting an input signal IN and transmitting the inverted signal onto an internal node 901, an inverter circuit 903 for inverting the signal on node 901 to produce an output signal OUT, and a capacitance element 902 connected between node 901 and a ground node.
Inverter circuits 900 and 903 have an identical CMOS arrangement, and the arrangement of inverter circuit 900 is representatively shown in FIG. 55. Inverter circuit 900 includes a P-channel MOS transistor (insulated gate type field effect transistor) PQ connected between a power-supply node and node 901 and receiving input signal IN at a gate, and an N-channel MOS transistor NQ connected between node 901 and a ground node and receiving input signal IN at a gate. These MOS transistors PQ and NQ have a resistance R when made conductive.
As shown in FIG. 56, when input signal IN is at a logic low or xe2x80x9cLxe2x80x9d level, node 901 is at a logic high or xe2x80x9cHxe2x80x9d level, and an electrode node, connected to node 901, of capacitance element 902 is charged to the power-supply voltage level. At this time, output signal OUT is at the L level.
When input signal IN rises to the H level, P-channel MOS transistor PQ transitions to the off state, while N-channel MOS transistor NQ attains the on state so that the accumulated charges in node 901 are discharged through MOS transistor NQ. The discharging rate of node 901 is determined by the capacitance value C of capacitance element 902 and the on-resistance (channel resistance when made conductive) R of MOS transistor NQ. When the voltage level of node 901 exceeds the input logic threshold voltage of inverter 903, output signal OUT rises from the L level to the H level.
On the other hand, when input signal IN falls from the H level to the L level, capacitance element 902 is charged via P-channel MOS transistor PQ. The rate at which the voltage level of node 901 rises is determined by the on-resistance R of MOS transistor PQ and capacitance value C of capacitance element 902. When the voltage level of node 901 exceeds the input logic threshold voltage of inverter 903, output signal OUT falls from the H level to the L level.
Thus, the time constant Rxc2x7C determined by capacitance value C of capacitance element 902 and the on-resistances R of MOS transistors PQ and NQ determines the charging/discharging rate of node 901, and the delay time xcfx84 of output signal OUT relative to input signal IN is determined depending on the charging/discharging rate of node 901.
In the arrangement of the delay circuit shown in FIG. 55, the delay time is determined by the on-resistances R of MOS transistors PQ and NQ and capacitance value C of capacitance element 902. The on-resistances R of MOS transistors PQ and NQ, however, depend on the power-supply voltage Vcc. In other words, in the case of the N-channel MOS transistor NQ, although the on-resistance R is the smallest when its gate voltage is at power-supply voltage Vcc in operation, the on-resistance itself depends on its gate to source voltage (the channel inversion layer attains a deeper on state as the gate to source voltage becomes larger). On the other hand, in the case of the P-channel MOS transistor PQ, the on-resistance R is the smallest when input signal IN is at the L level (the ground voltage level) in operation. The on-resistance of P-channel MOS transistor PQ also is dependent on the gate to source voltage, and thus, is dependent on the power-supply voltage Vcc.
There is a permissible range of xc2x15%, for instance, for the power-supply voltage Vcc. When exact precision is not required for delay time xcfx84, this permissible range of the power-supply voltage does not cause a significant problem. The timing adjustment in a semiconductor device operating at a high speed, however, requires the precision on the order of ns (nano seconds) for delay time xcfx84. In this case, the dependency of delay time xcfx84 on power-supply voltage Vcc cannot be neglected, and it becomes impossible to ensure the accurate internal operation even when the power-supply voltage Vcc is within its permissible range.
In addition, on-resistances R of MOS transistors PQ and NQ also depend on the operating temperature such that, in general, the on-resistances R becomes lower when the operating temperature rises.
Particularly, when the semiconductor device operates in synchronization with a clock signal as in the case of a clock synchronous semiconductor memory device, the internal timing must be matched accurately. The accurate internal operation, however, cannot be ensured if the delay time of the delay circuit fluctuates according to the fluctuation of the operating environment such as the power-supply voltage and the operating temperature.
An object of the present invention is to provide a delay circuit that has a low dependence on the fluctuation of the operating environment.
Another object of the present invention is to provide a delay circuit with suppressed fluctuation of the delay time regardless of the fluctuation of the operating environment.
A still another object of the present invention is to provide a delay circuit of high precision that is used for the timing adjustment of internal signals such as an internal clock signal and an internal control signal in a clock synchronous semiconductor memory device.
According to a first aspect of the present invention, the delay circuit includes a drive circuit for driving an output node according to a first input signal. The voltage level of the output signal from this drive circuit changes between a first voltage level and a second voltage level.
According to the first aspect of the present invention, the delay circuit further includes a capacitance element, a delay control circuit coupled between the output node and the capacitance element for isolating the capacitance element from the output node when a signal on the output node is between a first voltage level and a prescribed voltage level between the first voltage level and a second voltage level and for coupling the capacitance element to the output node when the signal on the output node is between the prescribed voltage level and the second voltage level, and an auxiliary drive circuit for driving the output node in a direction opposite to the potential driven direction of the output node by the drive circuit according to a second input signal leading in phase relative to the first input signal when activated. The auxiliary drive circuit is rendered active in response to the signal on the output node, and is rendered inactivate when the signal on the output node is between the first voltage level and the prescribed voltage level.
According to a second aspect of the present invention, the semiconductor circuit device includes a reference voltage generating circuit for generating a reference voltage onto an output node, and a gate circuit that has a power-supply transistor for supplying an operating current according to the reference voltage and generates an output signal according to an input signal. The reference voltage generating circuit includes a first resistance element connected between a first power-source node and a reference voltage output node, a second resistance element connected between the output node and an internal node, a first variable conductance element connected between a first input node and a second power-source node and having a conductance that changes according to the voltage of the reference voltage output node, and a second variable conductance element coupled between the reference voltage output node and the second power-source node and having its conductance change according to the voltage of the internal node.
According to a third aspect of the present invention, the delay circuit includes a plurality of cascaded inverter circuits and a plurality of auxiliary circuits each provided to a corresponding one of the output nodes of the plurality of inverter circuits and each for driving an output node of a corresponding inverter circuit in response to an output signal of an inverter circuit located downstream by an odd number of stages from the corresponding inverter circuit.
According to a fourth aspect of the present invention, the delay circuit includes a first inverter, a second inverter for inverting an output signal from the first inverter and a variable current source for supplying, to an output node of the first inverter, a current in a direction preventing the change of the output signal of the first inverter in response to an output signal from the second inverter. The variable current source includes a plurality of current supplying elements connected in parallel with one another. The plurality of current supplying elements are selectively rendered conductive by a control signal in the pseudo-gray code notation. In the pseudo-gray code notation, the values of the same digit of at least one bit are held at xe2x80x9c1xe2x80x9d in any two successive numeric values.
In the delay circuit, accurate delay time can be set by suppressing the change of the output signal from a delay inverter circuit of a preceding stage until the output signal from the inverter delay circuit of a succeeding stage is inverted in logic.
Moreover, the operating current of the delay circuit is determined by the reference voltage and the current of the output node is bypassed by the first and second variable conductance elements so that the fluctuation of the reference voltage in the fluctuation of the power-supply voltage can be suppressed. Accordingly, the operating current of the delay circuit can be made constant despite the fluctuation of the power-supply voltage so that the fluctuation of the delay time due to the fluctuation of the power-supply voltage can be suppressed.
In addition, a control signal of the pseudo-gray code notation is employed to control a variable current source transistor so that a significant current change can be prevented, and thus, the adjustment time in the delay time adjustment operation can be shortened. Moreover, the pseudo-gray code notation allows the previous current control state to be partially maintained. Consequently, the variable current source transistors are prevented from entering the off state all at the same time, which leads to preventing a rapid current change, and thus, the delay time adjustment can be performed in a stable manner.